Rapid Yield Estimation as a Computer Aid for Analog Circuit Design
نویسندگان
چکیده
A rapid yield estimation methodology that aids the analog circuit designer in making design trade-offs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulation, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage op amps, and has been incorporated into the Carnegie Mellon University (CMU) analog design system (ACACIA). An example of how ARYE allows analog designers to quickly explore the impact of design changes on yield will be presented. The primary goal of ARYE is to make numerous early predictions of parametric yield economical for the analog circuit designer.
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